This invention relates to a look-up table architecture. In particular, it relates to a technique for reducing the number of programmable architecture elements, such as SRAM cells, required, yet implements a look-up table which is capable of performing a limited number of specific multi-variable logic functions.
Look-up tables are highly configurable combinatorial logic devices. Their programming flexibility makes them desirable for use as basic building blocks in programmable logic devices (PLDs). Generally, a look-up table employs an array of programmable architecture elements, such as SRAM cells, to store data bits which are effectively used as output signals, each of the data bits corresponding to a particular set of input signals. A particular data bit is gated to the look-up table output terminal by means of logic gates which are controlled by the input signals (and their complements) to the look-up table. FIG. 1 is an illustration of the implementation of a generic 4-input look-up table.
The look-up table is controlled by 16 programmable SRAM cells 44, although any other type of memory device may be used. The output signal of each of these SRAM cells is applied to a respective one of 16 AND gates 80. Alternate ones of AND gates 80 are respectively controlled by the true and complement of the first data input J, the complement of input J being produced by inverter I1. The outputs of adjacent pairs of AND gates 80 are then combined by OR gates 81 and applied to eight AND gates 82. Alternate ones of AND gates 82 are respectively controlled by the true and complement of the second data input K, the complement of input K being produced by inverter I2. The outputs of adjacent pairs of AND gates 82 are combined by OR gates 83 and then applied to four AND gates 84. Alternate ones of AND gates 84 are respectively controlled by the true and complement of the third data input L, the complement of input L being produced by inverter I3. The outputs of adjacent pairs of AND gates 84 are combined by OR gates 85 and applied to two AND gates 86. One of AND gates 86 is controlled by the true of the fourth data input M, while the other AND gate 86 is controlled by the complement of that input, the complement of input M being produced by inverter I4. The outputs of AND gates 86 are combined by OR gate 87 to produce the data output. It will be apparent from the foregoing that any desired logical combination of data inputs J-M will produce a desired output from the SRAM cells 44.
The number of SRAM cells usually required to implement a look-up table depends upon the number of inputs to the look-up table. For a look-up table with n inputs, 2.sup.n SRAM cells are required to ensure that any function of n variables may be provided. It is often the case, however, that programmers of a particular PLD architecture use many of the look-up tables to perform a limited number of logic functions. For example, it is often the case that when a particular PLD is programmed, many of the look-up tables perform one of only three 4-variable functions--AND, OR, and XOR. In such a case, regardless of which of the three functions an individual programmer ultimately uses, some of the data bits stored in the 16 (2.sup.4) SRAM cells dedicated for the 4-input look-up table will be redundant across the entire range of possible outputs. As a result, SRAM cells, and therefore die space on the PLD, will be inefficiently used.
Thus, there is a need for a look-up table architecture and a technique which reduces the number of programmable architecture elements required to implement certain limited function look-up tables.